Hmmm I think I get it... The chip has these two pins which I believe are the ones I'm looking for :
Quote:
Pin 18 / nDRR / Data Received Reset / Active Low. When low, sets Data received Output Low (i.e. Clears DR)
Pin 19 / DR / Data Received / When High, Data has been received and placed on outputs RBR8:RBR1.
So I place an NOT gate on the DR connected to nDRR, so when it's activated it will get reseted. And another NOT gate from DR to CS. and plug WR directly to DR. What do you think... should this work?